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6 9.1 Building the Linux Application with Command Line Interface
This page provides instructions on the way to build various components in the Zynq PCIe Targeted Reference Design TRD approaches to setup the hardware platform and run the look on the ZC706 Evaluation Kit. The ZC706 Evaluation kit is determined by a XC7Z045 FFG900-2 Zynq-7000 All Programmable SoC AP SoC device. For further information, reference UG961.
1.1 About the Zynq PCIe TRD
The Zynq PCIe Targeted reference design expands the Base Targeted Reference Design UG925 with the addition of PCI Express communication that has a host system at PCIe x4 GEN2 speed. In the Base Targeted Reference design, the input from the video processing pipeline is generated by the test pattern generator inside FPGA fabric. In this design, the input from the video processing pipeline is generated by an application around the host computer at 1080p60 resolution and transmitted for the ZC706 board via PCIe. The data is processed by video pipeline and passed back for the host system via PCIe. As full 1080p60 video stream just take up around 4Gbps, yet another data generator along with a checker are implemented and linked to channel 1 of PCIe DMA showcasing the most PCIe x4 GEN2 bandwidth achieved from the hardware. For more info, please reference UG963.
1.2 Zynq PCIe TRD Package Contents The Zynq PCIe TRD package is released using the source code, Xilinx PlanAhead and SDK projects, with an SD card image which allows the user to operate the video demonstration and software program. It also includes the binaries needed to configure and boot the Zynq-7000 AP SoC board. The package also contains the software program driver source files required to operate application software within the PCIe host machine. This wiki page assumes anyone has already downloaded the PCIe TRD package and extracted its contents towards the PCIe TRD home directory known as as
with this wiki and towards the PCIe host machine inside a folder usually chosen.
The ZC706 Evaluation Kit ships while using version 14.x Device-locked to your Zynq-7000 XC7Z045 FFG900-2 unit and all required licenses to construct the TRD. For more information, consider UG798 ISE Design Suite 14: Installation and Licensing Guide.
PC with PCIe v2.0 slot. Recommended PCI Express Gen2 PC system motherboards are ASUS P5E Intel X38, ASUS Rampage II Gene Intel X58 and Intel DX58SO Intel X58.
Fedora 16 LiveCD for booting Linux on PCIe host machine.
A Linux development PC using the ARM GNU tools installed. The ARM GNU tools are included together with the Xilinx ISE Design Suite Embedded Edition or readily available for download separately.
A Linux development PC with all the distributed version control system Git installed. For more information, refer towards the UG821: Xilinx Zynq - 7000 EPP Software Developers Guide.
This section explains how you can generate the FPGA hardware bitsream while using Xilinx PlanAhead tool and ways to export the hardware platform to Xilinx Software Development Kit SDK for software content management. Inside the PlanAhead project, a Xilinx Platform Studio XPS project is referenced which contains the embedded hardware design. The design top level file instantiates the embedded top level file as well as the system with PCIe IP wrapper, PCIe DMA, PCIe performance monitor and hardware generator and checker blocks.
3.1 Building the Bitstream
On Windows 7, run using ISE Design Suite Command Prompt. Open ISE Design Suite Command Prompt by navigating Start All Programs Xilinx Design Tools 14.x ISE Design Suite 14.x Accessories.
In the Flow Navigator pane within the left-hand side under Program and Debug, click Generate Bitstream. The bitstream are going to be generated at
Note: A message window will turn up, saying you can find 5 critical warning messages. Ignore these warnings and press OK to continue together with the bitstream generation.
3.2 Exporting the Hardware Platform to SDK: Building Drivers for Zynq PS
From the PlanAhead menu bar, select File Export Export Hardware.
In the Export Hardware window press OK. The SDK hardware platform is going to be exported to
Note: If the Launch SDK choices checked inside Export Hardware window, SDK will probably be launched soon after SDK export has completed. This will not be recommended after all this.
This section explains the best way to import and build the First Stage Boot Loader FSBL plus the standalone OS based Board Support Package BSP from your provided SDK projects. A pre-compiled FSBL executable is found at
Note: The provided FSBL project is often a customized version in the FSBL SDK project template. The following features are already added to your Zynq PCIe TRD version:
On Windows 7, select Start All Programs Xilinx Design Tools 14.x ISE Design Suite 14.x EDK Xilinx Software Development Kit.
In the Workspace Launcher window, click Browse and navigate to
SDK projects to the SDK workspace, select File Import.
project needs a hardware platform SDK project generated by SDK export. Instead in the provided
project, one generated in Section 3.2 works extremely well. This requires anyone to update the project reference in the
project. This is just not recommended at this time.
In the Import wizard, expand the General folder, select Existing Projects into Workspace, and then click Next.
All projects are situated at the top-level as part of your SDK workspace. Click Browse and navigate to
The build process will begin automatically and builds the BSP first and so the FSBL. The generated Zynq FSBL executable are available at
This option could be changed by unchecking Project Build Automatically in the menu bar.
To manually build the project, right click
within the Project Explorer and select Build Project ; to clean up the project, select Clean Project.
This section explains tips on how to download the sources, configure, and build the U-boot boot loader with the Zynq PCIe TRD. A pre-compiled U-boot executable is found at
For more details, refer towards the Xilinx Zynq U-boot wiki. This step has a Linux development PC while using ARM GNU tools and Git installed see Section 3.2.
Clone the most up-to-date Zynq U-boot git repository from your Xilinx git server.
Create a different branch named zynqpcietrd143 determined by the Xilinx - 14.3-build2-trd tag. The Zynq PCIe TRD U-boot tag was made on top from the 14.3 release tag.
bash cd ZYNQTRDHOME/u-boot-xarm bash git checkout - b zynqpcietrd143 xilinx - 14.3-build2-trd
Apply the PCIe TRD specific patch on top on the Zynq PCIe TRD tag. The patch includes:
bash cp //copy the 14.3 TRD patch from package to dev PC bash git apply - -stat //display belongings in patch bash git apply - -check //check if patch could be applied bash git am //apply the patch
Configure U-boot to the Zynq ZC706 PCIe TRD.
Build the U-boot boot loader. The generated U-boot executable is found at
Rename this executable to This elf is needed for generating BOOT image.
is needed for SD boot mode to be able to program the QSPI device with TRD boot image and kernel images. The
contains the TRD bitstream. This section explains how to generate a boot image
from pre-compiled binaries provided with this package. The pre-compiled binaries are situated at
Alternatively, an individual can use the generated files from Sections 3.1, 4, and 5. Pre-generated boot images is available at
In the Create Zynq Boot Image dialog box, add the files
within the output folder field as shown inside figure. Press Create Image. This step will generate data named under
with the specified location.
Occasionally, an interior error message arises which may be safely ignored.
The order the place you add the files matters: it must be FSBL first, then bitstream, then u-boot.
from the final step as described above. User can rename the generated
This section explains tips on how to download the sources, configure, patch, and build the Linux kernel with the Zynq PCIe TRD. It also explains the best way to compile a tool tree. For more info, refer towards the Xilinx Zynq Linux wiki. This step needs a Linux development PC together with the ARM GNU tools and Git installed see Section 3 2.
7.1 Building the Linux Kernel Image
command is done during building U-BOOT and is also used to create Linux kernel image.
Clone the most up-to-date Zynq Linux kernel git repository from your Xilinx git server.
Create a brand new branch named zynqpcietrd143 Based for the xilinx - 14.3-build2-trd tag. The Zynq PCIe TRD Linux kernel tag is constructed on top from the 14.3 release tag.
bash cd ZYNQTRDHOME/linux-xlnx bash git checkout - b zynqpcietrd143 xilinx - 14.3-build2-trd
Configure the Linux kernel for your Zynq ZC706 PCIe TRD.
Build the Linux kernel. The generated kernel image can be obtained at
7.2 Building the Linux Device Tree Blob
This step mandates that the stages in Section 7.1 are completed first. Two pre-compiled Device Tree Blobs can be obtained at
Note that two device tree files are required within the TRD- the file is utilized to load image and Linux kernel image on the QSPI device using Linux OS and file can be used for loading Linux after QSPI programming is complete.
bash./scripts/dtc/dtc I dts O dtb f o bash./scripts/dtc/dtc I dts O dtb f o
For instructions concerning how to build the Zynq Root File System, please refer on the Xilinx Zynq Root File System Creation wiki. A pre-built ramdisk image is accessible at
Steps for building the To create image from, use following command Note that
script, a hook was included with execute a customized user script named
Our implementation of the script is situated at
One can modify this to improve the system behavior after boot up.
For example, to protect yourself from automatic oncoming of qt application to have Linux prompt after boot up:
zynqpcieqt carries a graphical user interface GUI implemented using Qt libraries along with the user navigates about the application with USB keyboard and mouse.
zynqpciecmd relies on a command line based menu where the consumer navigates the menu by typing into your UART terminal.
The following two sections explain how you can import and build each from the aforementioned video applications. The user should choose the style that is the best option for his or her purposes.
Note : In this tutorial, we are while using same SDK workspace such as Section 7 4. Hence the project explorer view is going to be pre-populated using the
SDK projects. However, the present project does not require some of these two projects; itrrrs very self-contained.
projects will probably be grayed out since they have already been added on your workspace already. Press Finish.
9.2 Building the Linux Application with Qt GUI
For building this project, anyone is needed to cross-compile the Qt and Qwt libraries for your Zynq platform. This step has a Linux development PC together with the ARM GNU tools installed see Section 3 2. For detailed instructions on the way to build these libraries, refer towards the Xilinx Zynq Qt Qwt Libraries - Build Instructions wiki.
Note: Some on the generated Qt utilities needed to build the applying are specific in your host platform. Hence, you will need to recompile if you are hoping to use a different host.
Note : In this tutorial, we are utilizing the same SDK workspace such as Section toc7 4. Hence the project explorer view will likely be pre-populated with all the
and - - should you have completed Section toc15 9.1 previously - - the
SDK projects. However, the present project does not require some of these projects; it only demands the Qt/Qwt libraries cross-compiled with the Zynq architecture in your host system and it is completely self-contained otherwise.
and - - should you have completed Section 9.1 previously - - the
For this project, please uncheck the Project Build Automatically option on the menu bar, or maybe you will receive a blunder message about the automatic build see next thing.
In the Project Explorer window, expand the
in your Qt/Qwt libraries install area refer towards the Xilinx Zynq Qt Qwt Libraries - Build Instructions wiki for details.
within the Project Explorer and select Build Project ; to completely clean the project, select Clean Project. The generated
The program compilation procedure is provided here.
CD. Likewise, Java compilation tools usually are not shipped as part with the Fedora 16 live CD. Hence, GUI compilation will require additional installations. The source code is provided for the end user to create upon this design; for TRD testing recompilation of application or GUI will not be recommended.
User may add debug messages or enable log verbose to help with debug.
IMPORTANT: Changes in data structure will even lead to changes within the GUI compilation, which is just not recommended.
Shared object files are generated on this same directory.
This section explains through step by step instructions how you can bring up the ZC706 board for video demonstration part on the TRD and running different video demonstrations out with the box.
The ZC706 Evaluation Kit carries with it an SD-MMC card pre-loaded with binaries that enable the consumer to run the recording demonstration and programs. It also includes the binaries essential to configure and boot the Zynq-7000 AP SoC based ZC706 board.
Note: If the evaluation kit design files were downloaded online, copy the full folder
from your package on the primary partition from the SD-MMC card and that is formatted as FAT32 utilizing a SD-MMC card reader for loading the QSPI device with boot image and Linux kernel image. Once QSPI programming ends, load
content on the primary partition from the SD-MMC card and that is formatted as FAT32 employing a SD-MMC card reader for booting Linux and loading the QT application.
11.1 Hardware Setup Requirements
Reference Design zip file containing file, Linux kernel and Linux filesystem binary files, devicetree binary and application ELF. Host system driver and GUI files
A control PC with ISE design Suite Logic Edition Tools v14.2
PC with PCIe v2.0 slot. Recommended PCI Express Gen2 PC system motherboards are ASUS P5E Intel X38, ASUS Rampage II Gene Intel X58 and Intel DX58SO Intel X58. Note the Intel X58 chipsets usually show higher performance. This PC may possibly also have Fedora Core 16 Linux OS attached with it.
Please realize that two PCs are essential for running this TRD. A control PC which can be connected towards the zc706 board via mini-USB running teraTerm and also a host PC running Fedora Core 16 Linux linked to zc706 via PCIe slot for the motherboard
Note: The example mentioned within this package is tested with X-58 and DX-79 PCIe Host machine along with a Dell model P2412H display monitor. However, the example should fully trust any HDMI-compatible output device.
For running the Host GUI and QT-based application on Zynq PS, please talk about Zynq-7000 All Programmable SoC ZC706 Evaluation Kit UG961.
11.3 Running the Host GUI and Qt-based GUI Application on Zynq PS For running the Host GUI and QT-based application on Zynq PS, please reference Zynq-7000 All Programmable SoC ZC706 Evaluation Kit UG961.
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The Zynq PCIe TRD package is released while using source code, Xilinx PlanAhead and SDK projects, as well as an SD card image that allows the user to own the video demonstration and software program. It also includes the binaries essential to configure and boot the Zynq-7000 AP SoC board. The package also contains the program driver source files required to operate application software within the PCIe host machine. This wiki page assumes anyone has already downloaded the PCIe TRD package and extracted its contents towards the PCIe TRD home directory known as
For more info, refer on the Xilinx Zynq U-boot wiki. This step needs a Linux development PC together with the ARM GNU tools and Git installed see Section 2.
Create a brand new branch named zynqpcietrd143 determined by the//Xilinx-14.3-build2-trd//tag. The Zynq PCIe TRD U-boot tag is created on top on the 14.3 release tag.
bash cd ZYNQTRDHOME/u-boot-xarm bash git checkout - b zynqpcietrd143 xilinx-14.3-build2-trd
Select Xilinx Tools Create Boot Image in the menu bar.
This section explains how you can download the sources, configure, patch, and build the Linux kernel with the Zynq PCIe TRD. It also explains how you can compile a tool tree. For more details, refer on the Xilinx Zynq Linux wiki. This step needs a Linux development PC using the ARM GNU tools and Git installed see Section 2.
Create a different branch named zynqpcietrd143 Based about the//xilinx-14.3-build2-trd//tag. The Zynq PCIe TRD Linux kernel tag is constructed on top from the 14.3 release tag.
bash cd ZYNQTRDHOME/linux-xlnx bash git checkout - b zynqpcietrd143 xilinx-14.3-build2-trd
To create image from, use following command Note that
Note : In this tutorial, we are with all the same SDK workspace like Section 4. Hence the project explorer view will likely be pre-populated with all the
For building this project, the consumer is forced to cross-compile the Qt and Qwt libraries with the Zynq platform. This step has a Linux development PC using the ARM GNU tools installed see Section 2. For detailed instructions regarding how to build these libraries, refer towards the Xilinx Zynq Qt/Qwt Libraries - Build Instructions wiki
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For IDS 14.4 release in the TRD please consider Zynq - 7000 PCIe Targeted Reference Design 14.4
9.1 Building the Linux Application with Command Line Interface
11.3 Running the Host GUI and Qt-based GUI Application on Zynq PS
This page provides instructions regarding how to build various components in the Zynq PCIe Targeted Reference Design TRD and the way to setup the hardware platform and run the design and style on the ZC706 Evaluation Kit. The ZC706 Evaluation kit is according to a XC7Z045 FFG900-2 Zynq - 7000 All Programmable SoC AP SoC device. For more info, talk about UG961.
The Zynq PCIe TRD package is released while using source code, Xilinx PlanAhead and SDK projects, with an SD card image which allows the user to operate the video demonstration and program. It also includes the binaries important to configure and boot the Zynq - 7000 AP SoC board. The package also contains the application driver source files required running application software inside the PCIe host machine. This wiki page assumes the person has already downloaded the PCIe TRD package and extracted its contents for the PCIe TRD home directory described as
The ZC706 Evaluation Kit ships while using version 14.x Device-locked on the Zynq - 7000 XC7Z045 FFG900-2 unit and all required licenses to construct the TRD. For more information, reference UG798 ISE Design Suite 14: Installation and Licensing Guide.
A Linux development PC together with the distributed version control system Git installed. For more information, refer on the Xilinx Git wiki also to UG821: Xilinx Zynq - 7000 EPP Software Developers Guide.
Create a fresh branch named zynqpcie trd143 depending on the//Xilinx - 14.3-build2-trd//tag. The Zynq PCIe TRD U-boot tag was made on top in the 14.3 release tag.
bash cd ZYNQ TRDHOME/u-boot-xarm bash git checkout - b zynqpcie trd143 xilinx - 14.3-build2-trd
Create a whole new branch named zynqpcie trd143 Based around the//xilinx - 14.3-build2-trd//tag. The Zynq PCIe TRD Linux kernel tag is constructed on top with the 14.3 release tag.
bash cd ZYNQ TRDHOME/linux-xlnx bash git checkout - b zynqpcie trd143 xilinx - 14.3-build2-trd
zynqpcie qt carries a graphical user interface GUI implemented using Qt libraries plus the user navigates across the application with USB keyboard and mouse.
zynqpcie cmd runs on the command line based menu where the consumer navigates the menu by typing into your UART terminal.
for your Qt/Qwt libraries install area refer on the Xilinx Zynq Qt/Qwt Libraries - Build Instructions wiki for details.
The ZC706 Evaluation Kit carries with it an SD-MMC card pre-loaded with binaries that enable anyone to run the playback quality demonstration and computer programs. It also includes the binaries important to configure and boot the Zynq - 7000 AP SoC based ZC706 board.
For running the Host GUI and QT-based application on Zynq PS, please consider Zynq - 7000 All Programmable SoC ZC706 Evaluation Kit UG961.
When using XILINX JTAG software like Impact, Chipscope and XMD on Linux, the proprietary kernel module windrvr from Jungo is was required to access the parallel- or usb-cable. As this module can not work with current linux kernel versions 2.6.18 a library originated, which emulates the module in userspace and allows the various tools to access the JTAG cable without resorting to a proprietary kernel module.
The library uses libusb to get into USB devices as well as the ppdev interface speak with parallel cables. The parallel part currently only supports Parallel Cable III mode and PCIV in PCIII compatibility mode because faster PCIV modes use another kernel module which isn't emulated with this library. So you are limited by a 200kHz JTAG clock when utilizing Parallel Cable IV using this software. The USB cable is supported at full speed.
Experimental support for FTDI 2232 based devices may be added. They are seen by Impact being a Parallel Cable III. These devices are significantly slower than another supported cable.
The library is named libusb-driver as it originated to support the USB cable, but later extended to also support parallel cables.
2008-03-26 : Xilinx has released their unique drivers dependant on libusb with ISE Design Suite 10.1. To use them, you need to create the environment-variable
before running the various tools. The driver on these pages no longer needs to get preloaded when you only used it gain access to USB cables. Parallel port support still usually rely on windrvr, which may be emulated by libusb-driver.
Using 32-bit ISE 10.1 on the 64-bit platform: When with all the 32-bit JTAG tools from ISE Design Suite 10.1 using a 64-bit machine, the instruments will not connect for the cable but output the next error: Cable operation just isn't supported when running the 32-bit version in the application using a 64-bit platform. To fix this, run the equipment with
or preload the most recent 32-bit version of libusb-driver. This will lead the knowhow to believe that they're running on the 32-bit platform and allows them for connecting to the cable.
2009-05-31 : ISE Design Suite 11.1 now uses Xilinxs libusb-based drivers as default, without the need to line
If you wish to use this driver with ISE 11.1 for USB cables and disable the builtin support for libusb, you now have to put
For parallel cables Xilinx still relies upon windrvr. This library works fine with parallel cables and ISE 11.1 without necessity for windrvr.
2010-03-15 : If you are using newer udev-versions much like the version a part of Debian Squeeze and Ubuntu 9.10, then this file is incompatible with this particular udev version. The effect of the is that the cable-firmware gets never loaded and also the cable led never fires up.
To fix this, run the next command as root:
You may need to reboot due to this change to be effective.
2010-05-22 : Support for ISE 12 is available inside the driver.
2011-05-08 : Support for ISE 13 has become available within the driver. A rewritten version of setuppcusb which preps modern distributions has become added.
Download to develop it, you have to have the libusb development package installed. It is known as libusb-dev on Debian.
Precompiled for Debian Etch, but better develop your own
xc3sprog, a suite of utilities for programming Xilinx FPGAs, CPLDs, and EEPROMs with all the Xilinx Parallel Cable and also other JTAG adapters under Linux
XUP by inisyn research, opensource JTAG programming for Spartan 3E core kit USB cable
USB JTAG adapter by Kolja Waschk, opensource integration from the XILINX platform cable USB into OpenOCD and openwince JTAG Tools
UrJTAG, open source jtag tools with basic support with the xilinx XPCU
2009-05-31 : ISE Design Suite 11.1 now uses Xilinx s libusb-based drivers as default, without the need to put
XILINX Platform Cable USB DLC9, DLC9LP and DLC9G